The present invention relates to a semiconductor fabrication technology and, more particularly, to a method of forming a landing plug contact of a semiconductor device.
As a semiconductor device becomes highly integrated, a space between gate patterns gets narrower so that a substrate portion for a landing plug contact, which is formed between the gate patterns, gets smaller. Since cell contact resistance continuously increases as a contact area decreases, a technology to reduce the cell contact resistance is necessary.
Accordingly, a pre-selective epitaxial growth (SEG) plug process has been used. In the pre-SEG plug process, an SEG plug having a given thickness is formed between the gate patterns before the landing plug contact is formed. After forming a gate spacer at sidewalls of the gate pattern before a formation of a cell spacer, a substrate is exposed by using the gate spacer as an etching barrier layer and the SEG plug is formed on the exposed substrate. Since a contact open area increases as much as a thickness of the cell spacer, the cell contact resistance decreases.
Meanwhile, in order to secure refresh characteristics of the semiconductor device, a technology of a recessed gate structure has been suggested, which is a 3D gate structure formed by recessing a region under the gate pattern to increase a channel length.
However, since there is no isolation layer which electrically insulates the recessed lower portion of the gate pattern from the SEG plug, an electrical short between the recess region and the SEG plug may occur (see FIG. 1). Such a phenomenon gets worse when an overlay of the gate pattern is done in the opposite direction to that of the recess region by misalignment.
If the thickness of the gate spacer is increased to solve such a limitation, there is a side effect in that a cell contact open area is reduced. Even in this case, there exists no isolation layer between the recess region and the SEG plug, an electrical insulation cannot be secured.